Siemens Digital Industrial Software announced the launch of Tessent IJTAG Pro, which completely changes the IJTAG input/output method based on IEEE 1687 by converting the original serial operation into parallel operation, while providing read and wr...
Siemens Digital Industrial Software announced the launch of Tessent IJTAG Pro, which completely changes the IJTAG input/output method based on IEEE 1687 by converting the original serial operation into parallel operation, while providing read and write access functions for customized hardware.
Siemens pointed out that this new software introduces high-bandwidth internal JTAG (IJTAG) and universal data streaming functions, and uses the wide bus of Siemens Tessent Streaming Scanning Network (SSN) software to increase data transmission speed, helping customers reduce test costs and shorten test time.
As transistor density continues to expand in multiple dimensions, the semiconductor industry is experiencing unprecedented rapid evolution. As semiconductor designs evolve from 2D architectures to 2.5D and even full 3D IC architectures, the challenges faced by design test increase exponentially. As the number of test vectors increases, vector execution time increases, ATE costs increase, and test pin resources are limited, it is crucial to optimize existing infrastructure to support test scale expansion if you want to maintain a competitive advantage in the design process.
Ankur Gupta, senior vice president and general manager of Siemens Digital Industrial Software Digital Design Creation Platform, pointed out that in today’s complex IC designs, optimizing test time is a major challenge. Tessent IJTAG Pro uses Siemens SSN architecture to convert traditional serial IJTAG operations into high-bandwidth parallel processing processes, which not only accelerates testing and reduces test-related costs, but also provides the flexibility required to innovate test access to meet the evolving needs of the industry.
Gupta said that as semiconductor design gradually upgrades from simple 2D architecture to complete 3D IC architecture, whether it is a single chiplet or an entire 3D IC package, testing costs can be saved through this software.
Srinivas Vooka, senior engineering manager at Google, pointed out that high-bandwidth IJTAG innovatively uses the SSN bus architecture, and its test vector transmission speed is far faster than the traditional serial method, which greatly shortens the test application time. The effect is particularly significant in built-in self-test (BIST) and mixed-signal IP testing.
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